Semiconductor wafer processing technologies including Gallium Arsenide (GaAs) and Indium Phosphide (InP) require improvements such as increased etching selectivity for a compound semiconductor wafer compared to a front-side metal layer. For example, as shown in FIG. 1, the thickness varies across a compound semiconductor wafer.
As such, to prevent punch-through of the compound semiconductor wafer to the front-side metal layer, a dry etching process needs to selectively etch the backside of the compound semiconductor wafer. FIG. 1 is an illustration showing a thickness difference across the compound semiconductor wafer. Specifically, FIG. 1 shows a ten micron thickness difference across the compound semiconductor wafer whereby a edge 6 thickness is within the range of approximately 60 μm to approximately 80 μm and a center 8 thickness is within the range of approximately 70 μm to approximately 90 μm. The creation of a via-opening in both edge 6 and center 8 of the compound semiconductor wafer requires complete etching through both center 8 and edge 6 without punching-through the front-side metal layer, i.e., etching wafer front-side metal layers 9A, 9B on a portion of the wafer.
Presently available etching processes are not selective enough to prevent punch-through of the front-side metal layer. As such, there is a need for a dry etching process that selectively etches the backside of the compound semiconductor wafer over the front-side metal layer, thereby preventing the front-side metal layer punch-through, even with compound semiconductor material thickness variations across the wafer, as well as providing other advantages over present etching processes, such as realizing an opening with vertical sidewalls, no undercutting the via-opening, and making a repeatable process.